Direct modulated vertical cavity surface emitting lasers (VCSELs) have become a standard technology for applications in local area networks (LANs) and storage area networks (SANs). VCSELs provide a number of advantages including desirable threshold current, divergence angle, and beam configuration. The surface emission property of VCSELs allows the devices to be manufactured in two-dimensional arrays and enables wafer level testing. Thus, VCSEL devices are not only efficient in operation, they are also relatively easy to manufacture having a relatively low fabrication cost. These advantages make the VCSEL ideally suited for high-volume, low-cost and short-reach data communication links.
For optical communication applications, high-modulation bandwidth is desirable. Supportable data rates vary directly with modulation bandwidth. Currently, VCSELs are commercially available that can support a data rate of 10 Gb/sec. For the next generation VCSEL applications, data rates of 17 Gb/sec. and beyond are desired. Principal factors affecting data rates of VCSEL devices include the relaxation oscillation frequency, optical nonlinearities, and parasitic circuit effects. Parasitic circuit effects are the direct result of device resistance and capacitance. Accordingly, one key area of VCSEL design optimizations involves techniques for reducing resistance and minimizing capacitance in the VCSEL.
Generally, a semiconductor-based light emitting device, such as a VCSEL, is formed by epitaxially growing semiconductor material layers over a substrate. Conventional techniques for minimizing device resistance include optimization of device resistance by doping the various epitaxially grown semiconductor material layers. Existing VCSEL designs also include a relatively thick dielectric layer underneath a contact pad and an isolation implant to make the semiconductor material between the electrical contact and the active region of the VCSEL electrically insulating, which can reduce the parasitic capacitance associated with the contact pad to negligible values. Conventional VCSEL arrangements further include an oxide layer for optical index guiding and current confinement in the region where carriers combine within the VCSEL to generate light. Both the isolation implant and the oxide layer are formed from material compositions that insulate or confine the injected current within the VCSEL. A conventional VCSEL device is illustrated in FIG. 1.
The conventional VCSEL 10 is a semiconductor device with an active region 14 arranged between vertically-stacked mirrors, commonly known as distributed Bragg reflectors (DBRs) or Bragg mirrors. The active region 14 is adjacent to an n-type DBR 12 along a lower surface and a p-type DBR 18 along a portion of an upper surface of the active region 14. The active region 14 includes quantum wells (not shown) that generate light in the presence of an injected current in an amount that reaches or exceeds a threshold level or VCSEL threshold current. The quantum wells are composed of thin layers of semiconductor materials that differ in band-gap energy. Each DBR or mirror is a structure formed from multiple layers of alternating materials with varying refractive index. Each layer boundary causes a partial reflection of the light emitted from the active region 14. For light having a wavelength that is close to four times the optical thickness of the layers, the multiple reflections combine with constructive interference, and the layers form a high-quality reflector. To achieve a desired reflectivity, the number of semiconductor or dielectric layers constituting each of the DBRs can be quite large. An isolation layer 15 surrounds the p-type DBR 18 and is between a p-type metal contact 11 and an oxide layer 16. The isolation layer 15, which can be formed by implanting ions of hydrogen, oxygen or other elements, limits the contact surface at the junction of the p-type DBR 18 and the p-type metal contact 11 and separates the p-type metal contact 11 from the active region 14. A dielectric layer 13 arranged between the p-type metal contact 11 and the isolation layer 15 limits the amount of p-type metal material in the VCSEL 10 and further separates a portion of the p-type metal contact 11 from the active region 14. The oxide layer 16 is below the isolation layer 15 and extends laterally beyond the isolation layer 15 into the p-type DBR 18 towards the center of the VCSEL 10. A gap in the isolation layer 15 defines an isolation aperture 24, which corresponds to the width of the p-type DBR 18. A gap in the oxide layer 16 defines an aperture 20 through which injected current flows from the p-type DBR 18 to the active region 14. In addition, to confining current flow through the region of the VCSEL 10 defined by the aperture 20, the oxide layer 16 also has a different refractive index than the semiconductor materials used to form the p-type DBR 18. For example, the refractive index of the p-type DBR 18 can be approximately 3.2 and the refractive index of the oxide layer 16 may be approximately 1.5. As a result, the oxide layer 16 provides refractive index guiding in the lateral direction in the region 19 of the device labeled optical mode.
The oxide layer 16 may be formed by oxidizing a semiconductor material layer that includes a significant amount of an element that is readily oxidized. For example, aluminum (Al) is an element that is frequently added to a semiconductor material layer to promote oxidation of the aluminum-containing layer. Generally, to form an aluminum-oxide layer, an aluminum-containing semiconductor layer is grown, and then heated in an oxidizing atmosphere, such as an atmosphere with high water vapor content. The oxidizing atmosphere oxidizes the exposed areas of any material having significant aluminum content.
Current injected into the VCSEL 10, as illustrated by arrows 26, flows from the p-type metal contact 11 into the p-type DBR 18. The isolation layer 15 and the oxide layer 16 are non-conducting and channel the current towards the aperture 20 in the optical region 19. When the current injected into the VCSEL 10 exceeds a threshold current electrons and holes recombine and emit photons in the optical region 19. Light is emitted from a relatively small area on the surface of the VCSEL 10, directly above or below the active region 14. The VCSEL 10 emits the light generated in the active region 14 through one of the p-type DBR 18 or the n-type DBR 12, dependent on which has a reflectivity less than that of the other. In the illustrated embodiment, the reflectivity of the p-type DBR 18 is less than the reflectivity of the n-type DBR 12. Accordingly, light is emitted from the VCSEL 10 in the upward direction as indicated by the arrow 25.
As illustrated in FIG. 1, the oxide layer 16 is not in contact with the active region 14. A thicker oxide layer extending towards the active region 14 would reduce capacitance in the VCSEL 10 due to the significantly lower dielectric constant of the oxidized material compared to the dielectric constant of the other layers of the semiconductor. However, such relatively thick oxide layers incur excess scattering losses, which significantly reduce the efficiency and effectiveness of the device. A thicker oxide layer also introduces excess mechanical stress into the device resulting in poor long term reliability performance. For optimal performance, the oxide layer 16 is located at a null of the optical standing wave in the p-type DBR 18. Consequently, the VCSEL 10 includes a gap 17 between an uppermost surface of the active region 14 and a lowermost surface of the oxide layer 16. Generally, the gap 17 or vertical separation distance between the active region 14 and the oxide layer 16 is on the order of 2,000 to 3,000 angstroms. Although the gap 17 is relatively small, the gap 17 provides a lateral leakage path underneath the oxide layer 16 and above the active region 14. The lateral leakage current, represented by arrows 30, results in a charge-pumped region outside the optical region 19. The charge-pumped region outside the optical region 19 increases monotonically with the amount of injected current or charge into the VCSEL 10. Accordingly, the unintended charge storage outside the region 19 contributes to the junction capacitance of the VCSEL 10, which can limit the modulation bandwidth and the supportable data rate of a conventional VCSEL device.
Tapered oxide layers have been introduced to reduce scattering loss and nonlinear damping in VCSELs resulting from interaction between lateral carrier and photon distribution non-uniformities. A tapered oxide layer that is thinnest in the region 19 and thickest at the lateral edges of the VCSEL has been shown to improve modulation bandwidth.